The present invention relates to integrated circuits and, more particularly, to a flying-cap type voltage level shifter.
A rising level shifter converts an input signal in a voltage domain having a supply voltage level VDDL to an output signal in a voltage domain having a supply voltage level VDDH, where VDDH is greater than VDDL. A flying-cap rising level shifter is a particular type of rising level shifter that employs a capacitor to increase the speed at which a transition in the input signal (from either high (i.e., logic 1) to low (i.e., logic 0) or from low to high) will appear as a similar or inverted transition in the output signal.
FIG. 1 is a schematic circuit diagram of a conventional flying-cap rising level shifter 100 that converts an input signal IN in a low-voltage domain VDDL to an output signal OUT in a high-voltage domain VDDH. The level shifter 100 has an inverter INV that operates in the low-voltage domain VDDL, and a p-type transistor (e.g., PMOS) P1 and a n-type transistor (e.g., NMOS) N1 that operate in the high-voltage domain VDDH. A capacitor C1 is realized using metals, MOS devices, or other suitable non-semiconductor/semiconductor devices.
In operation, the capacitor C1 is pre-charged to a voltage equivalent to the voltage difference between VDDH and VDDL, i.e., (VDDH-VDDL), using capacitor-charging circuitry (not shown in FIG. 1). If the input signal IN is initially high, then the output of the inverter INV will be low, the transistor N1 will be off, and the upper plate of the capacitor C1 and the gate voltage applied to the transistor P1 will be (VDDH-VDDL), which turns on the transistor P1 and drives the output signal OUT high. This does not work in case where the p-type threshold voltage Vtp>VDDL, but in that case, a normal inverter can be used for level shifting.
When the input signal IN goes from high to low, the output of the inverter INV and the lower plate of the capacitor C1 will be driven high. Since the capacitor C1 was pre-charged to (VDDH-VDDL), when the lower plate of the capacitor C1 is driven towards VDDL, the upper plate will be driven towards VDDH, which will turn off the transistor P1. At the same time, the output of the inverter INV being driven towards VDDL will turn on the transistor N1, which will drive the output signal OUT low.
When the input signal IN next switches from low to high, the output of the inverter INV will again be driven low, and the transistor N1 will turn off. At the same time, assuming that the capacitor C1 is still charged with a voltage difference of (VDDH-VDDL), when the lower plate of the capacitor C1 is driven low, the upper plate will be driven back towards (VDDH-VDDL), which will turn the transistor P1 back on, which will drive the output signal OUT back towards VDDH. And so on for subsequent transitions in the input signal IN.
As mentioned previously, the capacitor C1 is initially pre-charged to (VDDH-VDDL) using capacitor-charging circuitry that is not shown in FIG. 1. Not only does that capacitor-charging circuitry need to pre-charge the capacitor C1, but it must also make sure that the capacitor C1 stays charged to a desired voltage level, such as (VDDH-VDDL). Otherwise, inevitable parasitic leakage current will result in the capacitor C1 discharging to an undesired voltage level at which the transistor P1 will not be able to be switched off when the input signal IN transitions from high to low, and the level shifter 100 will not operate properly.
FIG. 2 is a schematic circuit diagram of a conventional cross-coupled pMOS-based rising level shifter 200 that converts an input signal IN in a low-voltage domain VDDL to an output signal OUT in a high-voltage domain VDDH. One of the disadvantages of the level shifter 200 is that the delay for transitions from low to high is typically significantly different from the delay for transitions from high to low. In other words, the time that it takes for a low-to-high transition in the input signal IN to be reflected in a low-to-high transition in the output signal OUT is typically significantly different from the time that it takes for a high-to-low transition in the input signal IN to be reflected in a high-to-low transition in the output signal OUT. This delay skew can lead to timing errors and data errors in downstream circuitry.